In circuit designs where high voltage (HV) or high current is present, it is generally necessary to take steps to reduce the potential risk to users of the electrical system. These steps traditionally include insulation, grounding, and the isolation of dangerous voltages and currents by galvanic isolation, being the technique of isolating functional sections of electrical systems to prevent current flow between them.
An isolation device prevents the propagation of DC and unwanted AC currents between its input and output while allowing the transmission of the desired AC signal. The isolation device accomplishes this function using an isolation barrier that has a high breakdown voltage and low leakage. A high resistive path exists across the isolation barrier, but the device can still transfer information in the desired AC signal across the isolation barrier by capacitive, inductive, or optical techniques.
Basic isolation provides protection against HV as long as the isolation barrier is intact. Basic isolation thus needs to be coupled to another basic isolation barrier for safety if human access is possible. Reinforced isolation is equivalent to two basic isolation barriers in series and is thus by itself sufficient as a safety barrier against HV. Most reinforced-isolation devices ensure safety using capacitive isolation technology under the worldwide standard VDE 0884 for magnetic and capacitive isolation-based reinforced-isolation. Capacitive isolators primarily use high-voltage silicon-dioxide (SiO2) capacitors to provide the isolation. With a dielectric strength of about 300 to 1,400 V/μm, SiO2 has the highest dielectric strength among commonly used HV isolation materials. Silicon nitride may also be used as part or all of the capacitor's dielectric.
One common reinforced-isolation device arrangement is a packaged multichip module, where each integrated circuit (IC) die in the package includes at least one embedded HV isolation capacitor (ISO cap), such as using two thick SiO2 capacitors connected in series by a bondwire between the input and the output that together constitute a double isolation barrier. The wafer fab process can be a high-performance analog or complementary metal-oxide-semiconductor (CMOS) process having multilevel metal levels, where the HV capacitor is formed between certain metal layers, and there is active circuitry formed in the semiconductor substrate or semiconductor surface (e.g., silicon) below the ISO capacitor.
Each ISO cap generally utilizes the top metal layer (say layer n) as its top plate and a lower metal layer (e.g., n-3 or lower) as its bottom plate, where the dielectric for the ISO cap comprises the respective interlevel dielectric (ILD) layers stacked on one another between the bottom and the top plate. Each ISO cap also includes a bond pad opening on its top plate for the top plate connection, and an indirect connection to its bottom plate is generally provided by circuitry from which the HV is being isolated. The bottom plate connector is typically coming from a digital signal generator or leads to a digital to analog converter (depending on which way the signal is going through the ISO cap) on the IC which creates or reads the signals which propagate across the isolation barrier. The bottom plate on one of the ISO caps is sourcing the signal to be sent across the isolation barrier, and the bottom plate on the other ISO cap (in series) is receiving this signal.
For the capacitive reinforced-isolation of the packaged multichip module, bondwires can be directly bonded to the top plate of the ISO cap on one die and to the top plate of the ISO cap on the other die, where there is a ball bond on one top plate and a stitch bond on the other top plate. Stitch bonding generally uses impulse welding or heat and pressure while feeding the wire through a hole in the center of the welding electrode. The first bond made during the assembly process referred to as a ball bond is made at one end of the bondwire to the top plate bond pad of the first ISO cap on the first die and is essentially normal (90°) to the plane of surface of the top plate. The other end (second formed end) of the bondwire includes a stitch bond that has a wire approach angle that is not normal to the plane of surface of the top plate bond pad of the second ISO cap of the second die, such as at an angle of about 30° to 40° relative to the surface of the top plate.